As speed requirements of computer systems have increased, systems employing greater numbers of parallel processors have been developed. One such system, has in the order of 64 parallel processors, see U.S. Pat. No. 3,537,074, issued Oct. 27, 1970 to R. A. Stokes et al, and assigned to the assignee of the present invention.
Present day large computer systems incorporating a high degree of parallelism often include a plurality of widely scattered registers. When data in these registers are to be compared, the propagation delays involved in transmitting data from each register to a central comparator and back consumes precious processing time and limits the overall throughput of the system.
Certain calculations in large parallel computer systems require the determination of which register(s) in a plurality of scattered registers are storing either the highest or lowest value numerical data.
When such numerical data is stored in either floating point or integer format, determination of which register is storing either the highest or the lowest data value requires complex parallel or time consuming serial data comparison.
Conversion of all data to binary equivalents greatly eases the comparison task but such comparison is in itself relatively complex and costly in terms of hardware or firmware. Great simplification is achieved in the overall determination task by merely converting the stored data to a binary representation which maintains the same relative magnitude ordering of the original stored data but not necessarily the exact binary equivalents thereof.
It is therefore an object of the present invention to provide a converter to transform a plurality of floating point or integer values into binary values of selectively the same or the inverse magnitude ordering.
It is a further object of the present invention to provide such a converter capable of implementation with relatively inexpensive components combined to function in a high speed efficient manner.